1. Field of the Invention
The present invention relates to a voltage generator circuit and, more particularly, to such a circuit generating and supplying a negative bias voltage to a substrate or well regions of a semiconductor memory device.
2. Description of the Prior Art
While a semiconductor device is supplied at its substrate and/or well region with a predetermined potential, in a dynamic random access memory (DRAM) device, a fixed negative potential is applied to the substrate or well regions thereof in which n-type MOS transistors are formed. This is because to reverse-bias a p-n junction formed between each of n-type source and drain regions of an n-type MOS transistors and the substrate or well regions. With the reverse-biased condition, the p-n junction has a smaller junction capacitance to thereby make each transistor operate at high speed. Thus, the DRAM device includes a voltage generator circuit generating and supplying the negative potential to the substrate or well regions.
The conventional negative voltage generator circuit consists of a low-potential signal generator circuit generating, in response to a clock signal oscillating between the supply potential (Vcc) and the ground potential (GND), a negative clock signal oscillating between GND and -Vcc, an output terminal connected to the substrate, and an output transistor consisting of a p-type MOS transistor with its source-drain path placed between the output terminal and the output terminal of the low-potential signal generator circuit. The output transistor turns on and off repeatedly in accordance with the negative clock signal applied to its gate, and the output terminal and accordingly the substrate are thus pulled down to a negative potential.
However, the output transistor is turned ON when applied at its gate with -Vcc level clock signal. For this reason, the output terminal (i.e., the substrate) is clamped at such a potential level that is higher than -Vcc level by the threshold level VTP of the output transistor, namely, -Vcc +.vertline.VTP.vertline.. For example, in the cases of Vcc being 3 volts and .vertline.VTP.vertline. being 1.5 volts, the voltage level of the output terminal, that is the substrate potential is clamped at -1.5 volts.
Such a small substrate bias voltage does not present the above-mentioned effects to the DRAM. Moreover, the small potential difference between the gate and source of the output transistor makes its driving oscillating small so that at takes long time to pull down the substrate to the predetermined potential.